As is known to those skilled in the art, a semiconductor memory device such as a dynamic random access memory (DRAM) cell comprises a plurality of memory cells which are used to store a large quantity of information. Each memory cell includes a capacitor for storing electric charge and a field effect transistor for opening and closing charge and discharge passages of the capacitor. The number of bits on DRAM chips has been increasing by approximately 4.times. every three years; this has been achieved by reducing the cell size. Unfortunately, the smaller cell size also results in less area to fabricate the capacitor.
In early DRAM generations, the storage electrode of each capacitor which constitutes each memory cell, together with each corresponding field effect transistor, was formed in the shape of a planar plate over the field effect transistor. Because of this planar plate shape, the storage electrode surface area was abruptly reduced as the cell size decreased. In this regard, conventional methods for fabricating memory cells have difficulties in increasing the surface area of storage electrodes because they involve the formation of a storage electrode having a planar plate shape.
In order to maintain increased electrode area while reducing the size of the memory cells, vertical gate (or trench) semiconductor memory structures have been employed. W. Hwang, et al. "High Density Vertical DRAM Cell", IBM Technical Disclosure Bulletin, Vol. 29, No. 5, October 1986, pp. 2335-2339 discloses a typical prior art high density vertical DRAM cell wherein the transfer device is oriented in the vertical direction and is positioned over the trench storage capacitor. A shallow trench filled with polysilicon or polycide serves as the MOS transfer device gate. A representation of the high density vertical trench DRAM cell disclosed in W. Hwang, et al. is reproduced herein in FIG. 1. Specifically, FIG. 1 comprises a semiconductor wafer containing a p.sup.+ substrate 10 and a p.sup.- epitaxial layer 12. The vertical DRAM cell also contains trenches 14 that contain an oxide/nitride/oxide liner 16 and n.sup.+ polysilicon 18. Atop of each trench 14 is crystalline n.sup.+ layer 20 and wordline 22 composed of n.sup.+ polysilicon positioned between each trench. A p-type epitaxial layer 24 is located on either side of wordline 22 and is formed on top of p.sup.- epitaxial layer 12 and n.sup.- polysilicon 18. The structure further includes bitlines 26 located on either sides of wordline 22 and field oxide regions 28.
In some instances, it is desirable to bury the bitline below the transfer gate, see for example, co-assigned U.S. application Ser. No. 08/787,418, filed Jan. 22, 1997, now U.S. Pat. No. 5,990,509. This bitline is often times formed in prior art processes by etching a trench within a thin film of As-doped oxide, blanket patterning a resist film in the bottom of the trench, etching the oxide film from the sidewalls of the trench where the transfer device will be, and annealing the substrate to drive the As dopant into the silicon wafer so as to form a buried bitline.
A major problem with this prior art approach is that the foregoing type of patterning produces conductive loops in the bitline effectively creating a common source. If a design will use uniquely addressed bitlines as also described in the above co-pending U.S. patent application Ser. No. 08/787,418, the loops need to be trimmed by a resist masking process.
One example of such a trim process is shown top-down in the sequence of FIGS. 2(a)-(d). In FIG. 2(a), the rows of pillars 2 are surrounded by deposition of arsenic containing glass 4. A lithographic mask 6 is printed in the resist (see, FIG. 2(b)) exposing only the ends of the loops to the isotropic etch of the dopant source resulting in the structure shown in FIG. 2(c). The high temperature drive will then diffuse arsenic into the silicon pillar forming two discrete diffused bitlines 8 on each side of the pillar as is shown in FIG. 2(d). Moreover, this prior art approach provides a poor control of channel doping with non-vertical pillars. In view of these drawbacks in prior art manufacturing of buried bitlines, there is a continued need to develop a new method of forming a buried bitline in a vertical semiconductor memory cell that does not have any conductive loops associated therewith. Such a method would eliminate the need of an extra processing step, in this case trimming via resist patterning, that is required by prior art processes to eliminate the conductive loops.